Nonvolatile memory cells using floating gate as the storage device are well known in the art. Nonvolatile memory cells using a floating gate for storage can be stacked gate type or split gate type. In a stacked gate cell, the cell has a first region and a second region spaced apart from one another in a semiconductor substrate with a channel region therebetween. A floating gate is spaced apart and insulated from the entire channel region, and controls the conduction of current in the channel region. A control gate is capacitively coupled and is spaced apart and insulated from the floating gate. The control gate is “stacked” on top of the floating gate—hence the term “stacked gate nonvolatile memory cell.”
In a stacked gate nonvolatile memory cell, programming occurs by either electrons being Fowler-Nordheim tunneled from the first region or the second region onto the floating gate or injected onto the floating gate through the mechanism of hot channel electron injection. The erase mechanism is for the electrons from the floating gate tunnel through an insulating layer either to the substrate, or to the first or second region.
In a split gate type nonvolatile memory cell, the floating gate is spaced apart and insulated from only a portion of the channel region. The control gate is over another portion of the channel region. Collectively, the operation of both the floating gate and the control gate is required to control the flow of current in the channel region. U.S. Pat. No. 5,029,130 discloses a split gate nonvolatile memory cell in which erasing occurs through the action of electrons from the floating gate being tunneled to an insulating layer to the control gate. The disclosure of U.S. Pat. No. 5,029,130 is hereby incorporated in its entirety by reference.
It is one of the objects of the present invention to improve upon the stacked gate nonvolatile memory cell of the prior art.